1. Field of the Invention
The invention relates in general to a method for improving an over erasing effect of a charge-trapping memory cell and a charge-trapping memory structure thereof, and more particularly to a method for improving an over erasing effect of a charge-trapping memory cell and a charge-trapping memory structure thereof capable of saving a layout area and the time of programming the over-erased cells.
2. Description of the Related Art
Electrically programmable and erasable non-volatile memories are used in various applications, and a charge-trapping memory or Nitride Read-Only Memory is also one of the non-volatile memories based on a charge trapping dielectric layer. Data is stored using the charge trapping dielectric layer such as a silicon nitride layer to trap charges. When negative charges are trapped, a threshold voltage of the memory cell increases. When the negative charges are removed from the charge trapping dielectric layer, the threshold voltage of the memory cell is decreased. This operation is referred to as the so-called erasing.
If the bias arrangement causes too many negative charges to be removed from the charge trapping dielectric layer, the threshold voltage of the memory cell becomes too low, and the memory cell is over erased, which causes the memory cell to generate a leakage current and thus influences the normal operation of the memory cell array.
FIG. 1 is a schematic illustration showing a conventional charge-trapping memory structure 100. Referring to FIG. 1, the charge-trapping memory structure 100 includes M word lines WL1 to WLM and a plurality of charge-trapping memory cell blocks. In FIG. 1, only one first charge-trapping memory cell block 110 and one second charge-trapping memory cell block 120 are illustrated without limitation. Each charge-trapping memory cell block includes a plurality of memory cells. Each memory cell includes a transistor, which is a floating gate field effect transistor.
In addition, each charge-trapping memory cell block further includes a plurality of bit lines BD each formed by buried diffusion. Each bit line BD is coupled to a switch SW, for example a bank select transistor. In addition, for example, multiple Y multiplexers correspond to one charge-trapping memory cell block. Each Y multiplexer is coupled to a sense amplifier 130 and corresponds to two bit lines BD. In the first charge-trapping memory cell block 110, a boundary abutting on the second charge-trapping memory cell block 120 has M boundary charge-trapping memory cells having transistors defined as boundary transistors BT1 to BTM. The bit line located in the first charge-trapping memory cell block 110 and coupled to the boundary transistors BT1 to BTM is defined as a first bit line BD1, and the bit line located in the second charge-trapping memory cell block 120 and coupled to the boundary transistors BT1 to BTM is defined as a second bit line BD2.
Typically, the erasing operations of the charge-trapping memory structure 100 are sequentially executed by each of the charge-trapping memory cell blocks. For example, the first charge-trapping memory cell block 110 cannot be erased until the second charge-trapping memory cell block 120 is erased. However, in the above-mentioned procedure, the boundary transistors BT1 to BTM perform two times of erasing operations. That is, the negative charges of each of the M boundary charge-trapping memory cells are removed twice. Consequently, it is possible to cause the too low threshold voltages of the M boundary charge-trapping memory cells and the over erased phenomenon is thus caused so that the charge-trapping memory structure 100 cannot be correctly read.
In addition, if the first charge-trapping memory cell block 110 is a repaired array block, the boundary transistors BT1 to BTM perform the erasing operations once after the second charge-trapping memory cell block is completely erased. However, because the M boundary charge-trapping memory cells are located in the repaired array block, they cannot receive program pulses after the erasing operations. Consequently, the M boundary charge-trapping memory cells will be over erased after the erasing operations such that the charge-trapping memory structure 100 cannot be correctly read. In addition, the over erased phenomenon enables the boundary transistors BT1 to BTM to generate leakage currents, which cause the sense amplifier 130 to see error currents through the Y multiplexers such that the verification of the charge-trapping memory structure 100 has errors. Furthermore, the effect caused by the over erased phenomenon mentioned above is more serious in a charge-trapping memory structure with high cycles.
FIG. 2 is a schematic illustration showing a conventional charge-trapping memory structure 200 with an isolating region. In the charge-trapping memory structure 200, an isolating region 240 is additionally disposed between a first charge-trapping memory cell block 210 and a second charge-trapping memory cell block 220. Consequently, the erasing operations of the first charge-trapping memory cell block 210 and the second charge-trapping memory cell block 220 cannot influence the charge-trapping memory cells on the boundary therebetween, so the boundary charge-trapping memory cells cannot be over erased. However, when the size of the charge-trapping memory structure 200 is large, the additional isolating region 240 wastes the layout area. In addition, it is usually necessary to add a STI (Shallow Trench Isolation) process to the manufacturing process to form the isolating region 240, thereby increasing the cost.
FIG. 3 is a schematic illustration showing a conventional charge-trapping memory structure 300 using a dummy cell. In the charge-trapping memory structure 300, an additional column of dummy cells 340 is disposed between a first charge-trapping memory cell block 310 and a second charge-trapping memory cell block 320. Consequently, the erasing operations of the first charge-trapping memory cell block 310 and the second charge-trapping memory cell block 320 cannot influence the charge-trapping memory cells on the boundary therebetween, and the boundary charge-trapping memory cells cannot be over erased. However, in the program pulse after erasing of the charge-trapping memory structure 300, the dummy cells have to be considered. So, extra pulses have to be increased, thereby deteriorating the behavior of the charge-trapping memory structure 300 and lengthening the program time.